Process for producing a silicon capacitor

ABSTRACT

To produce a silicon capacitor, hole apertures at whose surface a conductive zone (40) is formed by doping and whose surface is provided with a dielectric layer (6) and a conductive layer (7) are generated in an n-doped silicon substrate (1). To compensate for mechanical strains in the silicon substrate (1) brought about by the doping of the conductive zone (40), the conductive zone (40) is additionally doped with germanium which is outdiffused from a germanium-doped layer.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates generally to a process of producing acapacitor in a hole of a silicon substrate.

2. Description of the Related Art

European Patent Application EP 0 528 281 discloses a silicon capacitor.This comprises an n-doped silicon substrate whose surface is structuredin a characteristic way by an electrochemical etching in afluoride-containing, acidic electrolyte in which the substrate isconnected as an anode. In the electrochemical etching, more or lessregularly arranged hole structures form at the surface of the substrate.The hole structures have an aspect ratio up into the region of 1:1000.The surface of the hole structures is provided with a dielectric layerand a conductive layer. The conductive layer, dielectric layer andsilicon substrate form a capacitor in which, owing to the increase insurface brought about by the hole structures, specific capacitances ofup to 100 μFV/mm³ are achieved. In order to increase the conductivity ofthe substrate, it is proposed to provide an n⁺ -doped zone at thesurface of the hole structures.

Normally, silicon capacitors are produced in silicon wafers. In thisprocess, a bending of the silicon wafers is detected which is associatedwith mechanical strains due to the n⁺ -doped zone at the surface of thehole structures, which are up to 300 μm deep. This bending of thesilicon wafer results in problems in further process steps such aslithography, reduction in wafer thickness and chip separation, which arenecessary for incorporating the silicon capacitor in a package.

The publication by A. Fukuhara et al., J. Appl. Cryst. (1980), vol. 13,pages 31 to 33 discloses a study of the compensation for mechanicalstrains in silicon crystals. A strain is observed which is essentiallyproportional to the dopant concentration and which can be compensatedfor by an additional doping with germanium. Layers 1 to 5 μm deep aredoped with germanium and/or boron. The germanium is introduced bydiffusion, an annealing time of 14 days being necessary at a temperatureof 1473 degrees K.

The publication by A. Heuberger, Mikromechanik, Springer-Verlag 1989,pages 216-236 discloses that highly boron-doped silicon layers which areused as etch-stop layers in micromechanics and which are grownepitaxially on silicon substrates cause bends in substrates which arecompensated for by additionally introducing, for example, germanium intothe boron-doped layer.

SUMMARY OF THE INVENTION

The present invention provides a further method of producing a siliconcapacitor in which a bending of the silicon substrate is avoided andwhich can be used in a manufacturing process.

According to the present invention, this object is achieved by a methodof producing at least one silicon capacitor, wherein a multiplicity ofhole apertures is generated by electrochemical etching in a principalsurface of an n-doped silicon substrate, wherein a conductive zoneprovided with electrically active dopant is generated along the surfaceof the hole apertures, wherein a germanium-doped layer, by means ofwhich the conductive zone is doped with germanium, is generated on thesurface of the hole apertures, wherein a dielectric layer and aconductive layer are applied to the surface of the conductive zone, andwherein the conductive layer and the conductive zone are each providedwith a contact. Further developments of the invention include theconductive zone being doped with germanium by outdiffusion from thegermanium-doped layer. The germanium-doped layer is deposited by CVDdeposition at atmospheric pressure using a process gas containingGe(OCH₃)₄ and Si(OC₂ H₅)₄.

Preferably, a silicon layer which is doped with germanium in situ byadding a germanium-containing compound during the epitaxy is formed byepitaxy on the surface of the hole apertures. A further undoped siliconlayer is grown by epitaxy on the germanium-doped silicon layer, whereinthe conductive zone is formed in the germanium-doped silicon layer, inthe undoped silicon layer and in the adjacent surface of the holeapertures.

The electrically active dopant is introduced by outdiffusion into theconductive zone from a layer doped with the electrically active dopant.

In the preferred embodiment, the conductive zone is provided with adopant concentration of between 5.10¹⁹ cm⁻³ and 8.10²⁰ cm⁻³ forphosphorus and of between 5.10¹⁹ cm⁻³ and 5.10²¹ cm⁻³ for germanium orbetween 3.10¹⁹ cm⁻³ and 3.10²⁰ cm⁻³ for boron and 5.10¹⁹ cm⁻³ and 5.10²¹cm⁻³ for germanium.

In a method according to the invention, the electrochemical etching forforming the hole apertures is carried out in a fluoride-containing,acidic electrolyte with which the principal surface is in contact and avoltage is applied between the electrolyte and the silicon substrate insuch a way that the silicon substrate is connected as an anode, and aback of the silicon substrate situated opposite the principal surface isilluminated during the electrochemical etching.

In the method, the hole apertures are generated with diameters in therange between 0.5 μm and 10 μm and with depths in the range between 50μm and 300 μm, the hole apertures having an aspect ratio in the rangebetween 30 and 300. The dielectric layer is formed by combined formationof SiO₂ and Si₃ N₄ as a multilayer having a layer sequence SiO₂ /Si₃ N₄/SiO₂. The conductive layer is formed by gas-phase deposition of dopedpolysilicon.

In the method according to the invention, a multiplicity of holeapertures is generated in a principal surface of an n-doped siliconsubstrate by electrochemical etching. The electrochemical etchingpreferably takes place in a fluoride-containing, acidic electrolyte,with which the principal surface is in contact and a voltage is appliedbetween the electrolyte and the silicon substrate in such a way that thesilicon substrate is connected as an anode. In this process, a back ofthe silicon substrate which is opposite the principal surface isilluminated.

A conductive zone which is provided with electrically active dopant isgenerated along the surface of the hole apertures. In this connection,dopant which determines the conductivity of the conductive zone isdescribed as an electrically active dopant. In particular, phosphorous,boron or arsenic is used as an electrically active dopant.

A layer which is doped with germanium and which dopes the conductivezone with germanium is generated on the surface of the hole apertures.

According to a first embodiment, the conductive zone is generated byoutdiffusion of germanium from a layer doped with germanium. In theoutdiffusion from a germanium-doped layer, germanium is diffused to adepth of 0.2 to 0.5 μm at a temperature of 1400 degrees K. in 4 to 25hours. At a temperature of 1473 degrees K., a diffusion length of 0.2 μmis achieved after 0.56 hours and a diffusion length of 0.5 μm after 3.5hours. Such diffusion times are acceptable in a manufacturing process.

Preferably, the germanium-doped layer is formed from silicate glasswhich is deposited-in a CVD deposition at atmospheric pressure (APCVD)using a process gas containing Ge(OCH₃)₄ and Si(OC₂ H₅)₄.Germanium-doped silicate glass produced using this process gas and O₃ isdisclosed by S. Fisher et al., in the Solid Publication StateTechnology, Sept. 1993, pages 55 to 64. It was proposed an asintermediate oxide. The possibility of using it as a diffusion sourcefor germanium is not disclosed in the literature. In the methodaccording to the invention, O₂ or O₃ is added during the deposition. Theuse of O₂ means a process simplification. If O₃ is used an improved edgecoverage is achieved.

It is within the scope of the invention to diffuse germanium and theelectrically active dopant simultaneously into the surface of the holeapertures to produce the conductive zone.

In cases in which the diffusion length of the electrically active dopantis greater than that of germanium, it is advantageous to diffusegermanium with a time lead suitable for essentially overlapping thedoping profile of the germanium and the electrically active dopant inthe conductive zone. This is done, for example, by applying asilicate-glass layer which is doped with the electrical dopant, inparticular phosphorus, boron or arsenic and out of which theelectrically active dopant is outdiffused to the germanium-doped layerafter the lead time for the germanium diffusion. Alternatively, theelectrically active dopant may also be introduced by gas-phasediffusion.

To minimize mechanical stresses, it is within the scope of the inventionto carry out the germanium diffusion and the diffusion of theelectrically active dopant repeatedly. For this purpose, in particular,the layers used as dopant source are removed and applied again.

The germanium-doped layer is removed before a dielectric layer and anelectrically conductive layer on top of the latter are applied to thesurface of the conductive zone. The conductive layer and the conductivezone are each provided with a contact. The contacts may be arrangedeither in the region of the principal surface or on the principalsurface and the back.

According to another embodiment of the invention, a germanium-dopedsilicon layer is grown by epitaxy on the surface of the hole apertures.For this purpose, a germanium-containing compound, in particular GeH₄ isadded during the epitaxy step. The germanium-doped layer is preferablygrown in a thickness of between 10 and 100 nm. The electrically activedopant is then introduced by gas-phase diffusion or outdiffusion from alayer provided with the electrically active dopant. In this case, theconductive zone forms in the silicon layer grown during the epitaxy stepand the adjacent surface of the hole apertures. Temperature and time forthe outdiffusion of the electrically active dopant are chosen in such away that the divergent germanium profile is brought to coincidence withthe profile of the electrically active dopant.

According to a further embodiment, the electrically active dopant isincorporated in the lattice during the epitaxy step.

To equalize extremely different diffusion lengths of germanium and theelectrically active dopant, it is advantageous to deposit a furtherundoped silicon layer by epitaxy on the germanium-doped silicon layerbefore the electrically active dopant is driven in.

In this embodiment of the invention, the germanium-doped silicon layerand, optionally, the further silicon layer, which are grown by epitaxyremain on the surface of the hole apertures as part of the conductivezone. The dielectric layer and the conductive layer are then applied tothe surface of the conductive zone.

In the method according to the invention, the germanium doping isintended to compensate for the mechanical strain in the conductive zonecaused by the doping with electrically active dopant. Since the depth ofthe hole apertures is up to 300 μm and the total thickness of normallyused silicon wafers is around 600 μm, the mechanical strain in theconductive zone is associated with a noticeable bending of the wafer.The mechanical strains are brought about by the fact that, during thedoping, an electrically active dopant atom whose covalent bond radiusdiffers from that of the silicon atom is incorporated at asubstitutional lattice site in the silicon crystal. A phosphorus atomhas, for example a 6% smaller covalent bond radius in the siliconcrystal than a corresponding silicon atom, with the result that itcauses a contraction of the crystal lattice. This effect is thestronger, the higher the dopant concentration.

The lattice distortion may result in a high dislocation density. If amultiplicity of silicon capacitors is produced in a silicon wafer, awafer bending results. Since manufacturing systems which are normallyused, such as, for example, conventional lithography units, areexclusively designed for flat substrates, it is important, with a viewto optimized manufacturing yields, to avoid bending of substrate waferswhich is associated with the process.

In the method according to the invention, the disturbance of the latticeby the electrically active dopant is compensated for by an additionaldoping with germanium. In this process, the dopant concentrations areadjusted to one another in such a way that a bending is avoided. For aboron concentration of 1.1×10²⁰ cm⁻³, a germanium concentration of8×10²⁰ cm⁻³ is necessary for this purpose. Provided the distortion iselastic, there is a linear relationship between the two concentrations,i.e. lower boron concentrations require a correspondingly lowergermanium concentration. If phosphorus is used with a concentration of,for example, 1×10²⁰ cm⁻³, a germanium concentration of approximately1.2×10²⁰ cm⁻³ is adequate. Provided the maximum elastic distortionΔl_(max) /l of approximately 5×10⁻⁴ is not exceeded, the concentrationsnecessary are approximately proportional. However, as a result oflattice mismatch or exceeding the elastic range, other concentrationratios may also be needed to avoid the bending.

Germanium has the advantage that, on the one hand, it is electricallyneutral and, on the other hand, it has a high solubility in silicon andthat it has a greater covalent bond radius in the silicon crystal thanthe electrically active dopants boron and phosphorus which are normallyused to produce silicon components.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention is explained in greater detail below by reference toexemplary embodiments and the figures.

FIG. 1 is a side cross section which shows a silicon substrate with holeapertures.

FIG. 2 is a side cross section which shows the silicon substrate afterintroducing a germanium-doped layer and outdiffusing germanium.

FIG. 3 is a side cross section which shows the silicon substrate afterapplying a layer doped with an electrically active dopant andoutdiffusing said dopant.

FIG. 4 is a side cross section which shows a silicon substrate afterdeposition of a dielectric layer and of a conductive layer and formationof contacts to the conductive layer and the conductive zone.

FIG. 5 is a side cross section which shows a silicon substrate with holeopenings on whose surface a germanium-doped silicon layer is grown.

FIG. 6 is a side cross section which shows the silicon substrate aftergrowing a further undoped silicon layer and driving in electricallyactive dopant to form a conductive zone.

FIG. 7 is a side cross section which shows the silicon substrate afterdeposition of a dielectric layer and a conductive layer.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

A silicon substrate 1 composed of n-doped monocrystalline silicon havinga resistivity of 5 ohm×cm is provided with a multiplicity of holeapertures 2 at a principal surface 11 by electrochemical etching (seeFIG. 1).

For this purpose, the principal surface 11 is brought into contact withan electrolyte. A 6%-strength by weight hydrofluoric acid (HF) is forexample used as an electrolyte. A potential of 3 volts is applied to thesilicon substrate 1 as an anode. The silicon substrate 1 is illuminatedfrom a back 12 which is situated opposite the principal surface 11. Inthis process, a current density of 10 mA/cm² is set. In theelectrochemical etching, minority charge carriers migrate in the n-dopedsilicon to the principal surface 11, which is in contact with theelectrolyte. A space charge zone forms at the principal surface 11.Since the field strength in the region of depressions in the principalsurface 11 is greater than outside them, the minority charge carriersmigrate preferentially to these points. This results in a structuring ofthe principal surface 11. The deeper an initially small irregularity dueto etching is, the more minority charge carriers migrate to that pointand the stronger is the etching attack at this position.

The hole apertures 2 begin to grow outwards from the irregularities inthe principal surface 11, the irregularities being present with randomdistribution in any surface. To achieve a uniform distribution of thehole apertures 2, it is advantageous to provide the principal surface 11with irregularities in a controlled manner before the electrochemicaletching, which irregularities act as a nucleus for the etching attack inthe subsequent electrochemical etching. These irregularities can beproduced, for example, with the aid of conventional photolithography.

After an etching time of approximately 180 minutes, the hole apertures 2have a diameter of 2 μm, and having reached a depth of 175 μm. Thesilicon substrate 1 is then thoroughly rinsed with water.

A germanium-doped layer 3 is deposited at atmospheric pressure in a CVDmethod. The germanium-doped layer 3 is produced from doped silicateglass using a process gas containing Si(OC₂ H₅)₄, Ge(OCH₃)₄ and O₃.Atmospheric pressure and a temperature in the range 300° C. to 500° C.is set during this process. The germanium-doped layer 3 is deposited ina thickness of 100 nm to 300 nm (see FIG. 2).

In a heat-treatment step at 1400 degrees K., a germanium-doped zone 4 isgenerated in a diffusion time of 25 hr.

A layer 5 doped with an electrically active dopant is subsequentlydeposited on the germanium-doped layer 3 (see FIG. 3) in a CVD method.Boron or phosphorus, for example, is used as electrically active dopant.The doped layer 5 is deposited in a thickness of, for example, 100 nm.In a further heat-treatment step at 1400 degrees K., the electricallyactive dopant and the germanium are jointly driven in further. After adiffusion time of 2.5 hr., the dopant profiles of germanium and theelectrically active dopant coincide and form a conductive zone 40. Inthe case of boron, this takes approximately 9 hours. A dopantconcentration of 1.1×10²⁰ cm⁻³ for boron and 8×10²⁰ cm⁻³ for germaniumor 1×10²⁰ cm⁻³ for phosphorus and 1.2×10²⁰ cm⁻³ for germanium isestablished in the conductive zone 40. This achieves, on the one hand,an adequate conductivity of the doped zone 40, which forms a capacitorelectrode in the silicon capacitor and, on the other hand, effectivelyavoids a bending of the silicon substrate 1. The depth of the conductivezone 40 is, for example, 0.5 μm.

The germanium-doped layer 3 and the doped layer 5 are removed with10%-strength by weight hydrofluoric acid.

To produce the silicon capacitor, a dielectric layer 6 and a conductivelayer 7 are then applied and structured (see FIG. 4). The dielectriclayer 6 is preferably formed by combined generation of SiO₂ and Si₃ N₄as a multiple layer having a layer sequence SiO₂ /Si₃ N₄ /SiO₂, sincethis material has a sufficiently low defect density for a large-areacapacitor. The conductive layer 7 is formed, for example, from n⁺ -dopedpolysilicon. A first contact 8 is applied to the surface of theconductive layer 7 and a second contact 9 is applied to that surface ofthe doped zone 40 which is laid bare by structuring the dielectric layer6 and the conductive layer 7. The first contact 8 and the second contact9 are formed, for example, from aluminium.

In a further exemplary embodiment, hole apertures 2' are formed byelectrochemical etching in a principal surface 11' of a siliconsubstrate 1', as described by reference to FIG. 1 (see FIG. 5). Theresistivity of the silicon substrate 1' and the dimensions of the holeapertures 2' correspond to those described by reference to FIG. 1.

In an epitaxial reactor, a germanium-doped silicon layer 3' which has athickness of 10 to 100 nm is grown onto the surface of the holeapertures 2'.

The epitaxy takes place using SiH₂ Cl₂, GeH₄ and inert carrier gases ata temperature of 575° C. and a pressure of 66.7 Pa (0.5 torr). Themixing ratio of SiH₂ Cl₂ and GeH₄ is adjusted in such a way that thegermanium-doped layer 2' contains 10 atomic percent of germanium.

Using SiH₂ Cl₂ and inert carrier gases, an undoped silicon layer 4' isthen grown in the epitaxial reactor in a thickness of, for example, 20nm (see FIG. 6). In this process, a temperature of 650° C. and apressure of 66.7 Pa (0.5 torr) is maintained in the epitaxial reactor.

An electrically active dopant, for example boron or phosphorus, is thendiffused into the undoped silicon layer 4' and the germanium-dopedsilicon layer 3'. This takes place, for example, by gas-phase diffusionusing phosphine or borane. In this process, a temperature of 1400degrees K. is maintained. During the indiffusion of the electricallyactive dopant, a divergence of the germanium profile results in thegermanium-doped silicon layer 3'. During this process, germaniumdiffuses both into the undoped silicon layer 4' and into the adjacentsurface of the silicon layer 1'. The diffusion temperature and diffusiontime are adjusted in such a way that the electrically active dopant isdiffused precisely as far into the silicon substrate 1' as thegermanium. A doped zone 5' consequently forms at the surface of the holeapertures. The dopant profiles of the germanium and of the electricallyactive dopant extend over the undoped silicon layer 4', thegermanium-doped silicon layer 3' and the doped zone 5', which jointlyform a conductive zone 40'.

The indiffusion of the electrically active dopant can also take place bydepositing a suitably doped silicate-glass layer and outdiffusion fromthe silicate-glass layer, which has to be removed again after theoutdiffusion.

The silicon capacitor is produced by depositing a dielectric layer 6',for example, composed of SiO₂ /Si₃ N₄ /SiO₂ and a conductive layer 7'composed, for example, of n⁺ -doped polysilicon (see FIG. 7). Theconductive layer 7' and the conductive zone 40' are then provided withmetallic contacts (not shown). The contacts may both be arranged in theregion of the principal surface 11', a suitable structuring of thedielectric layer 6' and of the conductive layer 7' being necessary.Alternatively, one contact may be arranged on the conductive layer inthe region of the principal surface and one contact on a back situatedopposite the principal surface 11'.

Although other modifications and changes may be suggested by thoseskilled in the art, it is the intention of the inventors to embodywithin the patent warranted hereon all changes and modifications asreasonably and properly come within the scope of their contribution tothe art.

We claim:
 1. A method of producing at least one silicon capacitor,comprising the steps of:generating a multiplicity of hole apertures byelectrochemical etching in a principal surface of an n-doped siliconsubstrate, generating a conductive zone provided withelectrically-active dopant along a surface of said multiplicity of holeapertures, generating a germanium-doped layer, which dopes theconductive zone with germanium, on the surface of the hole apertures,applying a dielectric layer and a conductive layer to a surface of theconductive zone, and providing a contact for the conductive layer andfor the conductive zone.
 2. A method according to claim 1, wherein saidstep of generating said germanium-doped layer includes doping theconductive zone with germanium by outdiffusion from the germanium-dopedlayer.
 3. A method according to claim 2, wherein said step of generatingsaid germanium-doped layer includes CVD deposition at atmosphericpressure using a process gas containing Ge(OCH₃)₄ and Si(OC₂ H₅)₄.
 4. Amethod according to claim 1, wherein said step of generating saidgermanium-doped layer includes forming a silicon layer which is dopedwith germanium in situ by adding a germanium-containing compound duringan epitaxy step by epitaxy on the surface of the hole apertures.
 5. Amethod according to claim 4, further comprising the steps of:growing afurther undoped silicon layer by epitaxy on the germanium-doped layer,wherein said step of generating said conductive zone forms theconductive zone in the germanium-doped layer and in said further undopedsilicon layer and in the surface of said multiplicity of hole apertures.6. A method according to claim 1, wherein said step of generating theconductive zone introduces the electrically active dopant byoutdiffusion into the conductive zone from a layer doped with theelectrically active dopant.
 7. A method according to claim 1, whereinthe conductive zone is provided with a dopant concentration of between5.10¹⁹ cm⁻³ and 8.10²⁰ cm⁻³ for phosphorus and of between 5.10¹⁹ cm⁻³and 5.10²¹ cm⁻³ for germanium or between 3.10¹⁹ cm⁻³ and 3.10²⁰ cm⁻³ forboron and 5.10¹⁹ cm⁻³ and 5.10²¹ cm⁻³ for germanium.
 8. A methodaccording to claim 1, wherein said step of generating the multiplicityof hole apertures is carried out by electrochemical etching in afluoride-containing, acidic electrolyte with which the principal surfaceis in contact and applying a voltage between the electrolyte and thesilicon substrate in such a way that the silicon substrate is connectedas an anode, andilluminating a back of the silicon substrate situatedopposite the principal surface during the electrochemical etching.
 9. Amethod according to claim 8, wherein the hole apertures are generatedwith diameters in the range between 0.5 μm and 10 μm and with depths inthe range between 50 μm and 300 μm, the hole apertures having an aspectratio in the range between 30 and
 300. 10. A method according to claim1, wherein said step of applying said dielectric layer includes formingthe dielectric layer by combined formation of SiO₂ and Si₃ N₄ as amultilayer having a layer sequence SiO₂ /Si₃ N₄ /SiO₂.
 11. A methodaccording to claim 1, wherein the conductive layer is formed bygas-phase deposition of doped polysilicon.